seiko epson corporation 1 pf560-06 E0C623A 4-bit single chip microcomputer low voltage operation products l core cpu architecture l svd circuit l super low operating voltage (0.9v) l high quality display lcd driver n description the E0C623A is an advanced single-chip cmos 4-bit microcomputer consisting of the e0c6200a cmos 4-bit core cpu. it also contains the rom, ram, lcd driver circuit, time base counter and stopwatch counter. the E0C623A provides an excellent solution for low-power consumption systems with clock functions. n features l cmos lsi ............................................. 4-bit parallel processing l clock ..................................................... 32.768khz (typ.) l instruction set ........................................ 100 instructions l instruction cycle time ............................ 153sec, 214sec or 366sec (depending on instruction) l rom capacity ....................................... 1,024 12 bits l ram capacity ........................................ 80 4 bits l input port ............................................... 4 bits (pull-down resistors are available by mask option) l output port ............................................ 4 bits l serial i/f ................................................ 8 bits (clock sync.) l i/o port .................................................. 4 bits l lcd driver ............................................. 20 segments 3 commons, 1/3 duty or 4 commons, 1/4 duty (constant voltage power supply is built in) l built-in supply voltage detection (svd) circuit l interrupts ............................................... externa : input interrupt 1 line internal : timer interrupt 2 lines serial interface interrupt 1 line l supply voltage ...................................... 1.5v/3.0v (minimum operating voltage: 0.9v/1.8v) l current consumption ............................ halt mode : 1.0a/1.0a (typ.) operating mode : 2.5a/2.5a (typ.) l package ................................................ qfp12-48pin (plastic), qfp6-60pin (plastic) die form n line up model supply voltage 1.5v (0.9v to 2.0v) 3.0v (1.8v to 3.5v) e0c62l3a E0C623A clock 32khz (crystal or cr oscillation) 32khz (crystal or cr oscillation)
2 E0C623A n block diagram n pin configuration com0~3 v k00~03 p00~03 r00~03 sin dd osc1 osc2 reset seg0~19 test v l1~3 ca~cc v s1 v ss power controller lcd driver ram 80 words x 4 bits rom 1,024 words x 12 bits osc system reset control fout & buzzer interrupt generator input port test port i/o port output port timer stop watch serial interface svd sout sclk fout / buzzer buzzer core cpu e0c6200a qfp6-60pin 25 36 13 24 index 12 1 48 37 E0C623A 31 45 16 30 index 15 1 60 46 E0C623A 1 2 3 4 5 6 7 8 9 10 11 12 com2 com3 seg0 seg1 seg2 seg3 seg4 seg6 seg8 seg9 seg10 seg11 no. pin name 13 14 15 16 17 18 19 20 21 22 23 24 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 test p03 p02 p01 no. pin name 25 26 27 28 29 30 31 32 33 34 35 36 p00 n.c. reset k00 k01 k02 k03 r00 r01 r02 r03 v ss n.c. = no connection no. pin name 37 38 39 40 41 42 43 44 45 46 47 48 v dd osc1 osc2 v s1 ca cb cc v l1 v l2 v l3 com0 com1 no. pin name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 p00 n.c. reset k00 k01 k02 k03 r00 r01 r02 r03 n.c. n.c. v ss v dd no. pin name 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 osc1 osc2 v s1 n.c. n.c. ca cb cc n.c. v l1 v l2 v l3 com0 com1 com2 no. pin name 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 com3 n.c. seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 n.c. = no connection no. pin name 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 seg13 seg14 seg15 seg16 seg17 seg18 seg19 test n.c. n.c. n.c. n.c. p03 p02 p01 no. pin name qfp12-48pin
3 E0C623A n pin description v dd v ss v s1 v l1 v l2 v l3 ca?c osc1 osc2 k00?03 p00?03 r00?03 seg0? seg5 seg6 seg7 seg8?9 com0? reset test pin name i i o o o o i o i i/o o o o i i in/out power source (+) terminal power source (-) terminal oscillation and internal logic system regulated voltage output terminal lcd system regulated voltage output terminal (approx. -1.05 v) lcd system booster output terminal (v l1 x 2) lcd system booster output terminal (v l1 x 3) booster capacitor connecting terminal crystal or cr oscillation input terminal crystal or cr oscillation output terminal input terminal i/o terminal output terminal lcd segment output terminal (convertible to dc output by mask option) lcd common output terminal initial reset input terminal test input terminal qfp12-48pin 37 36 40 44 45 46 41?3 38 39 28?1 25?2 32?5 3? 8 9?0 47, 48, 1, 2 27 21 qfp6-60pin 15 14 18 25 26 27 21?3 16 17 4? 1, 60?8 8?1 33?7 38 39 40 41?2 28?1 3 53 pin no. function n electrical characteristics l absolute maximum ratings rating supply voltage input voltage (1) input voltage (2) operating temperature storage temperature soldering temperature / time permissible dissipation * 1 * 1: in case of plastic package (qfp12-48pin). symbol v ss v i v iosc topr tstg tsol p d value -5.0 to 0.5 v ss - 0.3 to 0.5 v ss - 0.3 to 0.5 -20 to 70 -65 to 150 260 c, 10sec (lead section) 250 unit v v v c c mw (v dd =0v) l recommended operating conditions E0C623A condition supply voltage oscillation frequency booster capacitor (1) booster capacitor (2) capacitor between v dd and v l1 capacitor between v dd and v l2 capacitor between v dd and v l3 capacitor between v dd and v s1 symbol v ss f osc1 f osc2 c1 c2 c3 c4 c5 c6 remark v dd =0v crystal oscillation cr oscillation, r=420k w unit v khz khz f f f f f f (ta=-20 to 70 c) max. -1.8 80 typ. -3.0 32.768 65 min. -3.5 0.1 0.1 0.1 0.1 0.1 0.1 e0c62l3a condition supply voltage oscillation frequency booster capacitor (1) booster capacitor (2) capacitor between v dd and v l1 capacitor between v dd and v l2 capacitor between v dd and v l3 capacitor between v dd and v s1 * 1: * 2: * 3: when the heavy load protection mode is set by software and the svd circuit is turned off. the voltage which can be displayed on the lcd panel will differ according to the characteristics of the lcd panel. when there is no software control during cr oscillation or crystal oscillation. symbol v ss f osc1 f osc2 c1 c2 c3 c4 c5 c6 remark v dd =0v * 3 v dd =0v, with software control * 1 crystal oscillation cr oscillation, r=420k w unit v v khz khz f f f f f f (ta=-20 to 70 c) max. -1.1 -0.9 * 2 80 typ. -1.5 -1.5 32.768 65 min. -2.0 -2.0 0.1 0.1 0.1 0.1 0.1 0.1
4 E0C623A l dc characteristics E0C623A unit v v v v a a a a ma ma ma ma a a a a a a (unless otherwise specified: v dd =0v, v ss =-3.0v, f osc =32.768khz, ta=25 c, v s1 /v l1 ? l3 are internal voltage , c1?6=0.1 f) max. 0 0 0.8? ss 0.85? ss 0.5 16 100 0 -1.0 -1.0 -3 -3 -300 typ. min. 0.2? ss 0.15? ss v ss v ss 0 5 30 -0.5 3.0 3.0 3 3 300 characteristic high level input voltage (1) high level input voltage (2) low level input voltage (1) low level input voltage (2) high level input current (1) high level input current (2) high level input current (3) low level input current high level output current (1) high level output current (2) low level output current (1) low level output current (2) common output current segment output current (during lcd output) segment output current (during dc output) symbol v ih1 v ih2 v il1 v il2 i ih1 i ih2 i ih3 i il i oh1 i oh2 i ol1 i ol2 i oh3 i ol3 i oh4 i ol4 i oh5 i ol5 v ih1 =0v, no pull down resistor v ih2 =0v, with pull down resistor v ih3 =0v, with pull down resistor v il =v ss v oh1 =0.1? ss v oh2 =0.1? ss (built-in protection resistance) v ol1 =0.9? ss v ol2 =0.9? ss (built-in protection resistance) v oh3 =-0.05v v ol3 =v l3 +0.05v v oh4 =-0.05v v ol4 =v l3 +0.05v v oh5 =0.1? ss v ol5 =0.9? ss condition k00?03, p00?03 reset, test k00?03, p00?03 reset, test k00?03, p00?03 k00?03 p00?03 reset, test k00?03, p00?03 reset, test r02, r03, p00?03 r00, r01 r02, r03, p00?03 r00, r01 com0?om3 seg0?eg19 seg0?eg19 e0c62l3a unit v v v v a a a a a a a a a a a a a a (unless otherwise specified: v dd =0v, v ss =-1.5v, f osc =32.768khz, ta=25 c, v s1 /v l1 ? l3 are internal voltage , c1?6=0.1 f) max. 0 0 0.8? ss 0.85? ss 0.5 16 100 0 -200 -200 -3 -3 -100 typ. min. 0.2? ss 0.15? ss v ss v ss 0 2.0 9.0 -0.5 700 700 3 3 130 characteristic high level input voltage (1) high level input voltage (2) low level input voltage (1) low level input voltage (2) high level input current (1) high level input current (2) high level input current (3) low level input current high level output current (1) high level output current (2) low level output current (1) low level output current (2) common output current segment output current (during lcd output) segment output current (during dc output) symbol v ih1 v ih2 v il1 v il2 i ih1 i ih2 i ih3 i il i oh1 i oh2 i ol1 i ol2 i oh3 i ol3 i oh4 i ol4 i oh5 i ol5 v ih1 =0v, no pull down resistor v ih2 =0v, with pull down resistor v ih3 =0v, with pull down resistor v il =v ss v oh1 =0.1? ss v oh2 =0.1? ss (built-in protection resistance) v ol1 =0.9? ss v ol2 =0.9? ss (built-in protection resistance) v oh3 =-0.05v v ol3 =v l3 +0.05v v oh4 =-0.05v v ol4 =v l3 +0.05v v oh5 =0.1? ss v ol5 =0.9? ss condition k00?03, p00?03 reset, test k00?03, p00?03 reset, test k00?03, p00?03 k00?03 p00?03 reset, test k00?03, p00?03 reset, test r02, r03, p00?03 r00, r01 r02, r03, p00?03 r00, r01 com0?om3 seg0?eg19 seg0?eg19
5 E0C623A l analog circuit characteristics and current consumption E0C623A (normal mode) * 1: the svd circuit is turned off. unit v v v v s a a (unless otherwise specified: v dd =0v, v ss =-3.0v, f osc =32.768khz, ta=25 c, c g =25pf, v s1 /v l1 ? l3 are internal voltage , c1?6=0.1 f) max. -0.95 2? l1 0.9 3? l1 0.9 -2.25 100 2.5 5.0 typ. -1.05 -2.40 1.0 2.5 min. -1.15 2? l1 -0.1 3? l1 -0.1 -2.55 characteristic internal voltage svd voltage svd circuit response time current consumption symbol v l1 v l2 v l3 v svd t svd i op condition connect 1m w load resistor between v dd and v l1 (without panel load) connect 1m w load resistor between v dd and v l2 (without panel load) connect 1m w load resistor between v dd and v l3 (without panel load) during halt during execution * 1 without panel load E0C623A (heavy load protection mode) * 1: the svd circuit is turned off. unit v v v v s a a (unless otherwise specified: v dd =0v, v ss =-3.0v, f osc =32.768khz, ta=25 c, c g =25pf, v s1 /v l1 ? l3 are internal voltage , c1?6=0.1 f) max. -0.95 2? l1 0.85 3? l1 0.85 -2.25 100 5.5 10.0 typ. -1.05 -2.40 2.0 5.5 min. -1.15 2? l1 -0.1 3? l1 -0.1 -2.55 characteristic internal voltage svd voltage svd circuit response time current consumption symbol v l1 v l2 v l3 v svd t svd i op condition connect 1m w load resistor between v dd and v l1 (without panel load) connect 1m w load resistor between v dd and v l2 (without panel load) connect 1m w load resistor between v dd and v l3 (without panel load) during halt during execution * 1 without panel load e0c62l3a (normal mode) * 1: the svd circuit is turned off. unit v v v v s a a (unless otherwise specified: v dd =0v, v ss =-1.5v, f osc =32.768khz, ta=25 c, c g =25pf, v s1 /v l1 ? l3 are internal voltage , c1?6=0.1 f) max. -0.95 2? l1 0.9 3? l1 0.9 -1.10 100 2.5 5.0 typ. -1.05 -1.20 1.0 2.5 min. -1.15 2? l1 -0.1 3? l1 -0.1 -1.30 characteristic internal voltage svd voltage svd circuit response time current consumption symbol v l1 v l2 v l3 v svd t svd i op condition connect 1m w load resistor between v dd and v l1 (without panel load) connect 1m w load resistor between v dd and v l2 (without panel load) connect 1m w load resistor between v dd and v l3 (without panel load) during halt during execution * 1 without panel load e0c62l3a (heavy load protection mode) * 1: the svd circuit is turned off. unit v v v v s a a (unless otherwise specified: v dd =0v, v ss =-1.5v, f osc =32.768khz, ta=25 c, c g =25pf, v s1 /v l1 ? l3 are internal voltage , c1?6=0.1 f) max. -0.95 2? l1 0.85 3? l1 0.85 -1.10 100 5.5 10.0 typ. -1.05 -1.20 2.0 5.5 min. -1.15 2? l1 -0.1 3? l1 -0.1 -1.30 characteristic internal voltage svd voltage svd circuit response time current consumption symbol v l1 v l2 v l3 v svd t svd i op condition connect 1m w load resistor between v dd and v l1 (without panel load) connect 1m w load resistor between v dd and v l2 (without panel load) connect 1m w load resistor between v dd and v l3 (without panel load) during halt during execution * 1 without panel load
6 E0C623A E0C623A (cr, normal mode) max. -0.95 2? l1 0.9 3? l1 0.9 -2.25 100 15.0 20.0 typ. -1.05 -2.40 8.0 15.0 min. -1.15 2? l1 -0.1 3? l1 -0.1 -2.55 * 1: the svd circuit is turned off. unit v v v v s a a (unless otherwise specified: v dd =0v, v ss =-3.0v, f osc =65khz, r cr =420k w , ta=25 c, v s1 /v l1 ? l3 are internal voltage , c1?6=0.1 f) characteristic internal voltage svd voltage svd circuit response time current consumption symbol v l1 v l2 v l3 v svd t svd i op condition connect 1m w load resistor between v dd and v l1 (without panel load) connect 1m w load resistor between v dd and v l2 (without panel load) connect 1m w load resistor between v dd and v l3 (without panel load) during halt during execution * 1 without panel load E0C623A (cr, heavy load protection mode) max. -0.95 2? l1 0.85 3? l1 0.85 -2.25 100 30.0 40.0 typ. -1.05 -2.40 16.0 30.0 min. -1.15 2? l1 -0.1 3? l1 -0.1 -2.55 * 1: the svd circuit is turned off. unit v v v v s a a (unless otherwise specified: v dd =0v, v ss =-3.0v, f osc =65khz, r cr =420k w , ta=25 c, v s1 /v l1 ? l3 are internal voltage , c1?6=0.1 f) characteristic internal voltage svd voltage svd circuit response time current consumption symbol v l1 v l2 v l3 v svd t svd i op condition connect 1m w load resistor between v dd and v l1 (without panel load) connect 1m w load resistor between v dd and v l2 (without panel load) connect 1m w load resistor between v dd and v l3 (without panel load) during halt during execution * 1 without panel load e0c62l3a (cr, normal mode) max. -0.95 2? l1 0.9 3? l1 0.9 -1.10 100 15.0 20.0 typ. -1.05 -1.20 8.0 15.0 min. -1.15 2? l1 -0.1 3? l1 -0.1 -1.30 * 1: the svd circuit is turned off. unit v v v v s a a (unless otherwise specified: v dd =0v, v ss =-1.5v, f osc =65khz, r cr =420k w , ta=25 c, v s1 /v l1 ? l3 are internal voltage , c1?6=0.1 f) characteristic internal voltage svd voltage svd circuit response time current consumption symbol v l1 v l2 v l3 v svd t svd i op condition connect 1m w load resistor between v dd and v l1 (without panel load) connect 1m w load resistor between v dd and v l2 (without panel load) connect 1m w load resistor between v dd and v l3 (without panel load) during halt during execution * 1 without panel load e0c62l3a (cr, heavy load protection mode) max. -0.95 2? l1 0.85 3? l1 0.85 -1.10 100 30.0 40.0 typ. -1.05 -1.20 16.0 30.0 min. -1.15 2? l1 -0.1 3? l1 -0.1 -1.30 * 1: the svd circuit is turned off. unit v v v v s a a (unless otherwise specified: v dd =0v, v ss =-1.5v, f osc =65khz, r cr =420k w , ta=25 c, v s1 /v l1 ? l3 are internal voltage , c1?6=0.1 f) characteristic internal voltage svd voltage svd circuit response time current consumption symbol v l1 v l2 v l3 v svd t svd i op condition connect 1m w load resistor between v dd and v l1 (without panel load) connect 1m w load resistor between v dd and v l2 (without panel load) connect 1m w load resistor between v dd and v l3 (without panel load) during halt during execution * 1 without panel load
7 E0C623A l oscillation characteristics the oscillation characteristics change depending on the conditions (components used, board pattern, etc.). use the follow- ing characteristics as reference values. E0C623A (crystal oscillation circuit) unit v v pf ppm ppm ppm v m w (unless otherwise specified: v dd =0v, v ss =-3.0v, crystal: c-002r (c i =35k w ), c g =25pf, c d =built-in, ta=25 c) max. 5 10 -3.5 typ. 20 min. -1.8 -1.8 -10 40 200 characteristic oscillation start voltage oscillation stop voltage built-in capacitance (drain) frequency/voltage deviation frequency/ic deviation frequency adjustment range harmonic oscillation start voltage permitted leak resistance symbol vsta vstp c d ? f/ ? v ? f/ ? ic ? f/ ? c g v hho r leak condition t sta 5sec t stp 10sec including the parasitic capacity inside the ic v ss =-1.8 to -3.5v c g =5 to 25pf c g =5pf between osc1 and v dd , v ss (v ss ) (v ss ) (v ss ) e0c62l3a (crystal oscillation circuit) * 1: items enclosed in parentheses ( ) are those used when operating at heavy load protection mode. unit v v pf ppm ppm ppm v m w (unless otherwise specified: v dd =0v, v ss =-1.5v, crystal: c-002r (c i =35k w ), c g =25pf, c d =built-in, ta=25 c) max. 5 10 -2.0 typ. 20 min. -1.1 -1.1(-0.9) * 1 -10 40 200 characteristic oscillation start voltage oscillation stop voltage built-in capacitance (drain) frequency/voltage deviation frequency/ic deviation frequency adjustment range harmonic oscillation start voltage permitted leak resistance symbol vsta vstp c d ? f/ ? v ? f/ ? ic ? f/ ? c g v hho r leak condition t sta 5sec t stp 10sec including the parasitic capacity inside the ic v ss =-1.1 to -2.0v (-0.9) * 1 c g =5 to 25pf c g =5pf between osc1 and v dd , v ss (v ss ) (v ss ) (v ss ) E0C623A (cr oscillation circuit) unit % v ms v (unless otherwise specified: v dd =0v, v ss =-3.0v, r cr =420k w , ta=25 c) max. 20 typ. 65khz 3 min. -20 -1.8 -1.8 characteristic oscillation frequency dispersion oscillation start voltage oscillation start time oscillation stop voltage symbol f osc vsta t sta vstp condition v ss =-1.8 to -3.5v (v ss ) (v ss ) e0c62l3a (cr oscillation circuit) unit % v ms v (unless otherwise specified: v dd =0v, v ss =-1.5v, r cr =420k w , ta=25 c) max. 20 typ. 65khz 3 min. -20 -1.1 -1.1 characteristic oscillation frequency dispersion oscillation start voltage oscillation start time oscillation stop voltage symbol f osc vsta t sta vstp condition v ss =-1.1 to -2.0v (v ss ) (v ss )
8 E0C623A c1 c2 c3 c4 c5 c c6 x'tal l1 l2 l3 dd s1 1.5v or 3.0v piezo buzzer r01 k00 k03 p00 p03 r00 r02 r03 i i/o o seg0 seg19 com0 com3 lcd panel E0C623A/62l3a coil g ca cb cc v v v v osc1 osc2 v reset test vss cp x'tal c g c1~c6 cp crystal oscillator trimmer capacitor capacitor capacitor 32.768khz ci(max.)=35k w 5~25pf 0.1 f 3.3 f n basic external connection diagram note: the above table is simply an example, and is not guaranteed to work. n package dimensions plastic qfp12-48pin plastic qfp6-60pin 14 0.2 17.6 0.4 31 45 14 0.2 17.6 0.4 16 30 index 0.35 0.1 15 1 60 46 2.7 0.1 0.1 3.1 max 1.8 0.85 0.2 0 10 0.15 0.05 0.8 unit: mm 7 ?.1 9 ?.4 25 36 7 ?.1 9 ?.4 13 24 index 0.18 12 1 48 37 1.4 ?.1 0.1 1.7 max 1 0.5 ?.2 0 10 0.125 ?.05 0.5 +0.1 ?.05
E0C623A notice: no part of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko ep son. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is n o representation that this material is applicable to products requiring high level reliability, such as, medical products. moreover, no license to an y intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accord ance with this material will be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject relating to strategic products under the control of the foreign exchange and foreign trade control law of japan and may require an export license from the ministry of international trade and industry or other approval from another government agency. ? seiko epson corporation 1999 all right reserved. seiko epson corporation electronic devices marketing division ic marketing & engineering group ed international marketing department i (europe & u.s.a.) 421-8, hino, hino-shi, tokyo 191-8501, japan phone : 042-587-5812 fax : 042-587-5564 ed international marketing department ii (asia) 421-8, hino, hino-shi, tokyo 191-8501, japan phone : 042-587-5814 fax : 042-587-5110
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